PIC16LC554-16CL View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LC554-16CL

EPROM-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C55X

6.4 Power-on Reset (POR), Power-up

Timer (PWRT), Oscillator Start-up

Timer (OST)

6.4.1 POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.6V – 1.8V). To

take advantage of the POR, just tie the MCLR pin

through a resistor to VDD. This will eliminate external

RC components usually needed to create Power-on

Reset. A maximum rise time for VDD is required. See

Electrical Specifications for details.

The POR circuit does not produce internal RESET

when VDD declines.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in RESET until the operating con-

ditions are met.

For additional information, refer to Application Note

AN607 “Power-up Trouble Shooting”.

6.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms (nominal)

timeout on power-up only, from POR. The Power-up

Timer operates on an internal RC oscillator. The chip is

kept in RESET as long as PWRT is active. The PWRT

delay allows the VDD to rise to an acceptable level. A

configuration bit, PWRTE can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-Up Time delay will vary from chip to chip and

due to VDD, temperature and process variation. See

DC parameters for details.

6.4.3

OSCILLATOR START-UP TIMER

(OST)

The Oscillator Start-Up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal

oscillator or resonator has started and stabilized.

The OST timeout is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

6.4.4 TIMEOUT SEQUENCE

On power-up, the timeout sequence is as follows: First

PWRT timeout is invoked after POR has expired, then

OST is activated. The total timeout will vary based on

oscillator configuration and PWRTE bit status. For

example, in RC mode with PWRTE bit erased (PWRT

disabled), there will be no timeout at all. Figure 6-7,

Figure 6-8 and Figure 6-9 depict timeout sequences.

Since the timeouts occur from the POR pulse, if MCLR

is kept low long enough, the timeouts will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 6-8). This is useful for testing purposes or

to synchronize more than one PIC16C55X device oper-

ating in parallel.

Table 6-5 shows the RESET conditions for some spe-

cial registers, while Table 6-6 shows the RESET condi-

tions for all the registers.

DS40143E-page 36

Preliminary

 1996-2013 Microchip Technology Inc.

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