PIC16C55X
FIGURE 10-8:
VDD
MCLR
Internal
POR
PWRT
Timeout
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
I/O Pins
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
30
33
32
31
34
34
TABLE 10-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param
No.
Sym
Characteristic
Min Typ† Max Units
Conditions
30 TmcL MCLR Pulse Width (low)
2000 —
— ns -40 to +85C
31
Twdt Watchdog Timer Timeout Period 7*
(No Prescaler)
18
33* ms VDD = 5.0V, -40 to +85C
32
Tost Oscillation Start-up Timer Period — 1024 — — TOSC = OSC1 period
TOSC
33 Tpwrt Power-up Timer Period
28*
72 132* ms VDD = 5.0V, -40 to +85C
34
TIOZ I/O hi-impedance from MCLR low
—
* These parameters are characterized but not tested.
2.0* s
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40143E-page 84
Preliminary
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