LTC1645CS View Datasheet(PDF) - Linear Technology
Part Name
Description
Manufacturer
LTC1645CS Datasheet PDF : 24 Pages
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LTC1645
APPLICATIO S I FOR ATIO
An external hard reset is initiated at time point 6. The ON
pin is forced below 0.8V but above 0.4V, and the GATEn
pin voltages start to ramp down. VOUTn also starts to ramp
down, and RESET goes low when VOUT2 drops below the
power-good trip level at time point 7.
Time points 8 to 15 are similar to time points 1 to 7, except
the ON pin’s different voltage thresholds are used to ramp
VOUT1 and VOUT2 separately. At time point 8, the ON pin
goes above 0.8V but below 2V, and one timing cycle later
(time point 9) GATE1 begins to ramp up with VOUT1
following one gate-to-source voltage drop lower. At time
point 10, the ON pin goes above 2V and GATE2 immedi-
ately begins ramping up with VOUT2 following one gate-to-
source voltage drop lower. As soon as VOUT2 reaches its
power-good trip level at time point 11, a timing cycle
starts. At the end of the timing cycle (time point 12),
RESET goes high and the power-up process is complete.
The ON pin is forced below 2V but above 0.8V at time point
13 and the GATE2 pin voltage starts to ramp down. VOUT2
also starts to ramp down and RESET goes low when VOUT2
drops below the power-good trip level at time point 14.
When the ON pin goes below 0.8V but above 0.4V at time
point 15, GATE1 and VOUT1 ramp down.
Time points 16 to 19 show the same power-up sequence
as time points 2 to 5, while time point 20 demonstrates the
GATEn pins being pulled immediately to ground (instead
of ramping down) by the ON pin going below 0.4V.
Power Supply Tracking and Sequencing Applications
The LTC1645 is able to sequence VOUTn in a number of
ways, including ramping VOUT1 up first and down last;
ramping VOUT1 up first and down first; ramping VOUT1 up
first and VOUT1 and VOUT2 down together; and ramping
VOUT1 and VOUT2 up and down together.
Figure 15 shows an application ramping VOUT1 and VOUT2
up and down together. The ON pin must reach 0.8V to
ramp up VOUT1 and VOUT2. The spare comparator pulls the
ON pin low until VCC2 is above 2.3V, and the ON pin cannot
reach 0.8V before VCC1 is above 3V. Thus, both input
supplies must be within regulation before a timing cycle
can start. At the end of the timing cycle, the output voltages
ramp up together. If either input supply falls out of
regulation, the gates of Q1 and Q2 are pulled low together.
Figure 16 shows an oscilloscope photo of the circuit in
Figure 15.
BOTH CURRENT LIMITS: 5A
VIN1
3.3V
0.01Ω*
VIN2
2.5V
10k
Q1
1/2 Si4920DY
Q2
10Ω
0.01Ω* 1/2 Si4920DY
10Ω
D1
1N4002
D2
1N4002
+
D3
MBR0530T1
+
VOUT1
3.3V
2.5A
CLOAD1
VOUT2
2.5V
2.5A
CLOAD2
4.99k
0.1µF
10k
14 13
12
12
3
25V
1%
TRIP
POINT:
VCC1 SENSE1 GATE1 VCC2 SENSE2 GATE2
10
ON
COMP+ 8
3V 1.82k
1%
1.18k
1%
4
FAULT
TIMER
LTC1645
(14-LEAD)
9
COMPOUT
6
FB
5
RESET
GND
1.18k
1%
1.37k
1%
1.37k
1%
11
7
0.33µF
µP RESET
*WSL1206-01-1% (VISHAY DALE)
1645 F15
Figure 15. Ramping 3.3V and 2.5V Up and Down Together
14
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