Z8018010PSC View Datasheet(PDF) - Zilog

Part Name

Description

Manufacturer

Z8018010PSC

ENHANCED Z180 MICROPROCESSOR

Zilog 

Z80180/Z8S180/Z8L180

Enhanced Z180 Microprocessor

DMA I/O ADDRESS REGISTER CHANNEL 1

(IAR1: I/O Address = 2BH to 2DH) specifies the I/O ad-

dress for channel 1 transfers. This may be destination or

source I/O address. The register contains 16 bits of I/O ad-

dress; its most significant byte identifies the Request

Zilog

Handshake signal and controls the Alternating Channel

feature.

All bits in IAR1B reset to 0.

Bit

7

6

5

A/T A/T

F

C

4

3

2

1

0

TOUT

/DREQ

Req 1 Sel

Figure 68. IAR MS Byte Register (IARIB: I/O Address 2DH)

DMA I/O Address Register Channel 1L

Mnemonic IAR1L

Address 2B

DMA I/O Address Register Channel 1B

Mnemonic IAR1B

Address 2D

Figure 69. DMA I/O Address Register Channel 1L

DMA I/O Address Register Channel 1H

Mnemonic IAR1H

Address 2C

Figure 71. DMA I/O Address Register Channel 1B

Figure 70. DMA I/O Address Register Channel 1H

1-54

PRELIMINARY

DS971800401

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