PIC16LC558-04/SO View Datasheet(PDF) - Microchip Technology
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PIC16LC558-04/SO Datasheet PDF : 108 Pages
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6.6 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (e.g., W register and STATUS
register). This will have to be implemented in software.
Example 6-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined at
0x20 in Bank 0 and it must also be defined at 0xA0 in
Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 6-1:
• Stores the W register
• Stores the STATUS register in Bank 0
• Executes the ISR code
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 6-1:
SAVING THE STATUS
AND W REGISTERS IN
RAM
MOVWF
SWAPF
BCF
MOVWF
:
:
:
SWAPF
MOVWF
SWAPF
SWAPF
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
;copy W to TEMP
;register, could be in
;either bank
;swap STATUS to be
;saved into W
;change to bank0
;regardless of
;current bank
;save STATUS to bank0
;register
STATUS_TEMP,W;swap STATUS_TEMP
;register into W, sets
;bank to original state
STATUS
;move W into STATUS
;register
W_TEMP,F
;swap W_TEMP
W_TEMP,W
;swap W_TEMP into W
PIC16C55X
6.7 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 6.1).
6.7.1 WDT PERIOD
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with tempera-
ture, VDD and process variations from part-to-part (see
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
6.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT timeout occurs.
2002 Microchip Technology Inc.
Preliminary
DS40143D-page 43
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