C8051F330-GP View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F330-GP

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F330/1/2/3/4/5

Table 10.1. Reset Electrical Characteristics

–40 to +85 °C unless otherwise specified.

Parameter

RST Output Low Voltage

RST Input High Voltage

RST Input Low Voltage

RST Input Pullup Current

VDD POR Threshold (VRST)

Missing Clock Detector Time-

out

Reset Time Delay

Minimum RST Low Time to

Generate a System Reset

VDD Monitor Turn-on Time

VDD Monitor Supply Current

Conditions

IOL = 8.5 mA,

VDD = 2.7 V to 3.6 V

RST = 0.0 V

Time from last system clock

rising edge to reset initiation

Delay between release of any

reset source and code

execution at location 0x0000

Min

—

0.7 x VDD

—

—

2.40

100

5.0

15

100

—

Typ

—

—

—

25

2.55

220

—

—

—

20

Max Units

0.6

V

—

V

0.3 x VDD

40

µA

2.70

V

600

µs

—

µs

—

µs

—

µs

50

µA

104

Rev. 1.5

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