C8051F330-GP View Datasheet(PDF) - Silicon Laboratories
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C8051F330-GP Datasheet PDF : 216 Pages
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C8051F330/1/2/3/4/5
13.4. System Clock Selection
The internal oscillator requires little start-up time and may be selected as the system clock immediately fol-
lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ-
ically require a start-up time before they are settled and ready for use. The Crystal Valid Flag (XTLVLD in
register OSCXCN) is set to '1' by hardware when the external oscillator is settled. In crystal mode, to
avoid reading a false XTLVLD, software should delay at least 1 ms between enabling the external
oscillator and checking XTLVLD. RC and C modes typically require no startup time.
The CLKSL[1:0] bits in register CLKSEL select which oscillator source is used as the system clock.
CLKSL[1:0] must be set to 01b for the system clock to run from the external oscillator; however the exter-
nal oscillator may still clock certain peripherals (timers, PCA) when the internal oscillator is selected as the
system clock. The system clock may be switched on-the-fly between the internal oscillator, external oscilla-
tor, and Clock Multiplier so long as the selected clock source is enabled and has settled.
SFR Definition 13.5. CLKSEL: Clock Select
R
R
R
R
R
R
R/W
R/W
Reset Value
-
-
-
-
-
-
CLKSL1 CLKSL0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
0xA9
Bits7–2:
Bits1–0:
UNUSED. Read = 000000b, Write = don't care.
CLKSL[1:0]: System Clock Source Select Bits.
00: SYSCLK derived from the Internal High-Frequency Oscillator and scaled per the IFCN
bits in register OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the Internal Low-Frequency Oscillator and scaled per the OSCLD
bits in register OSCLCN.
11: reserved.
Rev. 1.5
123
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