C8051F330-GP View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

C8051F330-GP

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F330/1/2/3/4/5

SFR Definition 7.1. REF0CN: Reference Control

R

R

R

R

R/W

R/W

R/W

R/W

Reset Value

-

-

-

-

REFSL TEMPE BIASE REFBE 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0 SFR Address:

0xD1

Bits7–4:

Bit3:

Bit2:

Bit1:

Bit0:

UNUSED. Read = 0000b; Write = don’t care.

REFSL: Voltage Reference Select.

This bit selects the source for the internal voltage reference.

0: VREF pin used as voltage reference.

1: VDD used as voltage reference.

TEMPE: Temperature Sensor Enable Bit.

0: Internal Temperature Sensor off.

1: Internal Temperature Sensor on.

BIASE: Internal Analog Bias Generator Enable Bit.

0: Internal Bias Generator off.

1: Internal Bias Generator on.

REFBE: Internal Reference Buffer Enable Bit.

0: Internal Reference Buffer disabled.

1: Internal Reference Buffer enabled. Internal voltage reference driven on the VREF pin.

64

Rev. 1.5

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