CDB42L50 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
Manufacturer
CDB42L50 Datasheet PDF : 48 Pages
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CS42L50
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25° C; VL = 1.7 V - 3.3 V; Inputs: logic 0 = GND, logic 1 = VL, CL = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 17)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL
trc
-
Fall Time of SCL
tfc
-
Rise Time of SDA
trd
-
Fall Time of SDA
tfd
-
Setup Time for Stop Condition
tsusp
4.7
Max
Unit
100
KHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
25
ns
25
ns
1
µs
300
ns
-
µs
Note: 17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
Stop
S ta rt
R epeated
S ta rt
SDA
t buf
t hdst
t high
t hdst
tf
SCL
t low t hdd
t sud
t sust
tr
Figure 3. Control Port Timing - I2Câ
Stop
t susp
14
DS544PP1
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