CS48500 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

Manufacturer

CS48500

32-bit Audio Decoder DSP Family

Cirrus Logic 

CS48500 Data Sheet

32-bit Audio Decoder DSP Family

5.15 Switching Characteristics — Digital Audio Output Port

Parameter

Symbol

Min

Max

Unit

DAO_MCLK period

DAO_MCLK duty cycle

DAO_SCLK period for Master or Slave mode1

DAO_SCLK duty cycle for Master or Slave mode1

Tdaomclk

40

-

40

Tdaosclk

40

-

40

-

ns

60

%

-

ns

60

%

Master Mode (Output A1 Mode)1,2

DAO_SCLK delay from DAO_MCLK rising edge,

DAO_MCLK as an input

tdaomsck

-

DAO_LRCLK delay from DAO_SCLK transition, respectively3

tdaomstlr

-

T DAO1_DATA[3..0], DAO2_DATA[1..0]

delay from DAO_SCLK transition3

tdaomdv

-

F Slave Mode (Output A0 Mode)4

DAO1_DATA[3..0], DAO2_DATA[1..0]

A delay from DAO_SCLK transition3

tdaosdv

19

ns

8

ns

10

ns

15

ns

R 1.Master mode timing specifications are characterized, not production tested.

2.Master mode is defined as the CS48500 driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input,

D it is divided to produce DAO_SCLK, DAO_LRCLK.

3.This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK

is the point at which the data is valid.

L I 4.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.

NTIALPH Tdaomclk

E E DAO_MCLK

ID D DAO_SCLK

F tdaomdv , tdaosdv

NDAOn_DATAn

O tdaomstlr

C DAO_LRCLK

tdaomsck

tdaomstlr

Figure 11. Digital Audio Port Timing, MCLK Master Mode

22

©Copyright 2006 Cirrus Logic, Inc.

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