PSD4242G2V-12UIT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD4242G2V-12UIT
STMicroelectronics
PSD4242G2V-12UIT Datasheet PDF : 89 Pages
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PSD4235G2
Table 39. Port Operating Modes
Port Mode
Port A
MCU I/O
Yes
PLD I/O
McellA Outputs
Yes
McellB Outputs
No
Additional Ext. CS Outputs
No
PLD Inputs
Yes
Port B
Yes
Yes
Yes
No
Yes
Port C
Yes
No
No
Yes
Yes
Address Out
No
No
No
Address In
Yes
Yes
Yes
Data Port
No
No
No
Peripheral I/O
Yes
No
No
JTAG ISP
No
No
No
MCU Reset Mode2
No
No
No
Note: 1. Can be multiplexed with other I/O functions.
2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.
Port D
Yes
Port E
Yes
Port F
Yes
Port G
Yes
No
No
No
No
No
No
No
No
No
No
Yes
No
Yes
No
Yes
No
No
Yes (A7 – 0)
Yes (A7 – 0)
Yes (A7 – 0)
or (A15 – 8)
Yes
No
Yes
No
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes1
No
No
No
No
Yes
Yes
Table 40. Port Operating Mode Settings
Mode
Defined in PSDsoft
Express
Control
Register
Setting
Direction
Register
Setting
VM Register
Setting
JTAG Enable
1 = output,
MCU I/O
Declare pins only
0 (Note 4)
0 = input
N/A
N/A
(Note 2)
PLD I/O
Declare pins and
Logic equations
N/A
(Note 2)
N/A
N/A
Selected for MCU
Data Port (Port F, G) with non-multiplexed N/A
N/A
N/A
N/A
bus
Address Out
(Port E, F, G)
Declare pins only
1
1 (Note 2)
N/A
N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for Input
N/A
Macrocells
N/A
N/A
N/A
Peripheral I/O
(Port F)
Logic equations
(PSEL0 and PSEL1)
N/A
N/A
PIO bit = 1
N/A
JTAG ISP 3
Declare pins only
N/A
N/A
N/A
JTAG_Enable
MCU Reset Mode Specific pin logic level N/A
N/A
N/A
N/A
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port E.
4. Control Register setting is not applicable to Ports A, B and C.
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