PSD4246F3V-70UT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD4246F3V-70UT

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Figure 29. Port A, B and C Structure

DATA OUT

Register

DQ

WR

MCELL7-MCELL0 (Port A)

MCELLB7-MCELLB0 (Port B)

Ext.CS (Port C)

READ MUX

P

D

B

DATA OUT

OUTPUT

MUX

DATA IN

OUTPUT

SELECT

ENABLE OUT

PORT Pin

DIR Register

DQ

WR

ENABLE PRODUCT TERM (.OE)

INPUT

MACROCELL

CPLD - INPUT

Enable Out. The Enable Out register can be read

by the MCU. It contains the output enable values

for a given port. A 1 indicates the driver is in output

mode. A 0 indicates the driver is in tri-state and the

pin is in input mode.

Ports A, B and C – Functionality and Structure

Ports A, B and C have similar functionality and

structure, as shown in Figure 29. The ports can be

configured to perform one or more of the following

functions:

s MCU I/O Mode

AI04936

s CPLD Output – Macrocells McellA7-McellA0

can be connected to Port A. McellB7-McellB0

can be connected to Port B. External Chip

Select (ECS7-ECS0) can be connected to Port

C or Port F.

s CPLD Input – Via the Input Macrocells (IMC).

s Address In – Additional high address inputs

using the Input Macrocells (IMC).

s Open Drain/Slew Rate – pins PC7-PC0 can be

configured to fast slew rate. Pins PA7-PA0 can

be configured to Open Drain mode.

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