FDC37C78-HT View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

FDC37C78-HT

Floppy Disk Controller

Microchip Technology 

Default

28H

90H

00H

70H

CR00

CR01

CR02

CR03

00H

CR04

00H

CR05

FFH

CR06

00H

CR07

00H

CR08

00H

CR09

00H

CR0A

00H

CR0B

00H

CR0C

78H

CR0D

00H

CR0E

00H

CR0F

00H

CR10

00H

CR11

00H

CR12-

CR1E

00H

CR1F

Table 33 - Configuration Registers

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Valid

Reserved

OSC

Reserved

FDC PWR

PDEN

Reserved

Lock CRx

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IDENT

MFM

DRVDEN 1 Reserved

Reserved

Enhanced

FDC Mode 2

Reserved

Reserved

Reserved

EXTx4

DRV 0X1

DEN SEL

DMA Mode

Reserved

Floppy Drive D

Floppy Drive C

Floppy Drive B

Floppy Drive A

Auto Power Management

Media ID Polarity

Floppy Boot Drive

Reserved

Reserved Reserved Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

FDD3-DRTx

FDD2-DRTx

FDD1-DRTx

FDD0-DRTx

Reserved

Device ID/ 78H

Device Revision/00

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Test

Reserved

FDD3-DTx

FDD2-DTx

FDD1-DTx

FDD0-DTx

Configuration Register Description

The configuration registers consist of the

Configuration Select Register (CSR) and

Configuration Registers CR00 - CR1F. The

configuration select register is written to by writing

to port +0. The Configuration Registers CR00;

CR1F are accessed by reading or writing to port

+1.

Configuration Select Register (CSR)

This register can only be accessed when the

chip is in the Configuration Mode. This register,

located at port +0, must be initialized upon

entering the Configuration Mode

before the configuration registers can be

accessed and is used to select which of the

Configuration Registers are to be accessed at port

+1.

Configuration Registers CR00 -CR1F

These registers are set to their default values at

power up and are not affected by RESET (except

where explicitly defined that a hardware reset

causes that bit to be reset to default). They are

accessed at port +1. Refer to the following

descriptions for the function of each configuration

register.

64

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