TDA7580(2002) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
TDA7580 Datasheet PDF : 31 Pages
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TDA7580
SPI INTERFACE
Figure 8. SPI Timings
SS
MISO
MOSI
SCL
(CPOL=0,CPHA=0)
Valid
Valid
tsetup
tdtr
tsssetup
tsclkl
thold
tsshold
tsclkh
tsclk
Symbol
TDSP
tsclk
tdtr
tsetup
thold
tsclkh
tsclkl
tsssetup
tsshold
tsclk
tdtr
tsetup
thold
tsclkh
Description
Internal DSP Clock Period (Typical 1/74.1MHz)
MASTER
Minimum Clock Cycle
Minimum Sclk edge to MOSI valid
Minimum MISO setup time
Minimum MISO hold time
Minimum SCK high time
Minimum SCK low time
Minimum SS setup time
Minimum SS hold time
SLAVE
Minimum Clock Cycle
Minimum Sclk edge to MOSI valid
Minimum MOSI setup time
Minimum MOSI hold time
Minimum SCK high time
Value
13.495
12*TDSP
40
16
9
0.5*tsclk
0.5*tsclk
40
25
12*TDSP
40
16
9
0.5*tsclk
18/31
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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