ML6430/ML6431
REGISTER DATA
BIT
DESCRIPTION
VALUE RANGE
BIT CODE
RANGE
0
0
PulsePol 0 CSYNC Polarity
0
1 PulsePol 1 H/V Blank Polarity
High Active-Low Active
High Active-Low Active
0 or 1
0 or 1
0
2 PulsePol 2 S/B Clamp Polarity
High Active-Low Active
0 or 1
0
3 Clk 4X
Select 4X Clock
Low 1X Clock = 13.5MHz
High 4X Clock = 54MHz
0 or 1
1
0 Pixel0
Pix Counter Load Bit 0
1
1 Pixel1
Pix Counter Load Bit 1
1
2 Pixel2
Pix Counter Load Bit 2
1
3 Pixel3
Pix Counter Load Bit 3
2
0 Pixel4
Pix Counter Load Bit 4
2
1 Pixel5
Pix Counter Load Bit 5
2
2 Pixel6
Pix Counter Load Bit 6
2
3 Pixel7
Pix Counter Load Bit 7
3
0 Pixel8
Pix Counter Load Bit 8
3
1 Pixel9
Pix Counter Load Bit 9
Numerical value taken as unsigned
binary. Actual no. of pixels is:
512 + P 10:0
2
nom = ~011 0000 0000
max = 011 0011 0000
min = 010 1101 0000
Do not vary pixel [10:0] by more than
±6% from nominal.
1024 > no. of pixels > 512 and
fNOM x 1.06 > fNEW > fNOM x 0.94
3
2 Pixel10
Pix Counter Load Bit 10
3
3 Burst
Burst Gate Enable
Low = Back Porch Clamp
High = Burst Gate
0 or 1
4
0
CSyncRaw (or CSYNC Regen)
4
1 RawClamp (or Clamp Regen)
Low = regenerated CSYNC
High = raw CSYNC
Low = regenerated Clamp
High = raw Clamp
0 or 1
0 or 1
4
2 TTL Sync TTL horizontal + vertical
Low = sync separator active
Sync Input
High = TTL horiz + vert sync input
0 or 1
4
3 WideBlank (or Narrow)
Low = narrow blanking
High = wide blanking
0 or 1
5
0 HDelay0
H Delay parameter allows
5
1 HDelay1 moving the entire constellation
0000000 to 1111111:
5
2
HDelay2
of output pulses relative to the
incoming HSYNC. Exception: 7-bit Horizontal Delay parameter.
0000000 means –64p
5
3 HDelay3 Sync Tip clamp may be
Values:
6
0
HDelay4
selected for delay or triggered –64p< Hdly < 63p, p = 1/F4XCLK
from incoming sync
1111111 means +63p
6
1 HDelay5 depending on application.
1000000 means 0p
6
2 HDelay6
6
3 Noise Gating 3/4 line lockout
Low = noise gating on
High = noise gating off
0 or 1
Table 10. ML6430 Register Map
18