PIC12F635/PIC16F636/639
2.2.2.6 PCON Register
The Power Control (PCON) register (see Table 12-3)
contains flag bits to differentiate between a:
• Power-on Reset (POR)
• Wake-up Reset (WUR)
• Brown-out Detect (BOD)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the Ultra Low-Power
Wake-up and software enable of the BOD.
The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0
U-0
R/W-0
R/W-1
R/W-x
U-0
—
—
ULPWUE SBODEN(1) WUR
—
bit 7
R/W-0
POR
R/W-x
BOD
bit 0
bit 7-6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
ULPWUE: Ultra Low-Power Wake-up Enable bit
1 = Ultra Low-Power Wake-up enabled
0 = Ultra Low-Power Wake-up disabled
SBODEN: Software BOD Enable bit(1)
1 = BOD enabled
0 = BOD disabled
WUR: Wake-up Reset Status bit
1 = No Wake-up Reset occurred
0 = A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs)
Unimplemented: Read as ‘0’
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOD: Brown-out Detect Status bit
1 = No Brown-out Detect occurred
0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
Note 1: BODEN<1:0> = 01 in the Configuration Word register for SBODEN to control the
Brown-out Detect module.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
© 2005 Microchip Technology Inc.
Preliminary
DS41232B-page 25