M4-256/32-10VC View Datasheet(PDF) - Lattice Semiconductor
Part Name
Description
Manufacturer
M4-256/32-10VC Datasheet PDF : 46 Pages
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MACH 4 TIMING PARAMETERS OVER OPERATING RANGES1
-7
-10
-12
-14
-15
-18
Min Max Min Max Min Max Min Max Min Max Min Max Unit
Combinatorial Delay:
tPDi Internal combinatorial propagation delay
tPD Combinatorial propagation delay
Registered Delays:
5.5
8.0
10.0
12.0
13.0
16.0 ns
7.5
10.0
12.0
14.0
15.0
18.0 ns
tSS Synchronous clock setup time, D-type register
tSST Synchronous clock setup time, T-type register
tSA Asynchronous clock setup time, D-type register
tSAT Asynchronous clock setup time, T-type register
tHS Synchronous clock hold time
tHA Asynchronous clock hold time
tCOSi Synchronous clock to internal output
tCOS Synchronous clock to output
tCOAi Asynchronous clock to internal output
tCOA Asynchronous clock to output
Latched Delays:
5.5
6.0
7.0
10.0
10.0
12.0
ns
6.5
7.0
8.0
11.0
11.0
13.0
ns
3.5
4.0
5.0
8.0
8.0
10.0
ns
4.5
5.0
6.0
9.0
9.0
11.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
ns
3.5
4.0
5.0
8.0
8.0
10.0
ns
3.5
4.5
6.0
8.0
8.0
10.0 ns
5.5
6.5
8.0
10.0
10.0
12.0 ns
7.5
10.0
12.0
16.0
16.0
18.0 ns
9.5
12.0
14.0
18.0
18.0
20.0 ns
tSSL Synchronous Latch setup time
6.0
7.0
8.0
10.0
10.0
12.0
ns
tSAL Asynchronous Latch setup time
4.0
4.0
5.0
8.0
8.0
10.0
ns
tHSL Synchronous Latch hold time
0.0
0.0
0.0
0.0
0.0
0.0
ns
tHAL Asynchronous Latch hold time
4.0
4.0
5.0
8.0
8.0
10.0
ns
tPDLi Transparent latch to internal output
8.0
10.0
12.0
15.0
15.0
18.0 ns
tPDL Propagation delay through transparent latch to output
10.0
12.0
14.0
17.0
17.0
20.0 ns
tGOSi Synchronous Gate to internal output
4.0
5.5
8.0
9.0
9.0
10.0 ns
tGOS Synchronous Gate to output
6.0
7.5
10.0
11.0
11.0
12.0 ns
tGOAi Asynchronous Gate to internal output
9.0
11.0
14.0
17.0
17.0
20.0 ns
tGOA Asynchronous Gate to output
11.0
13.0
16.0
19.0
19.0
22.0 ns
Input Register Delays:
tSIRS Input register setup time
tHIRS Input register hold time
tICOSi Input register clock to internal feedback
Input Latch Delays:
2.0
2.0
2.0
2.0
2.0
2.0
ns
3.0
3.0
3.0
4.0
4.0
4.0
ns
3.5
4.5
6.0
6.0
6.0
6.0 ns
tSIL Input latch setup time
tHIL Input latch hold time
tIGOSi Input latch gate to internal feedback
tPDILi Transparent input latch to internal feedback
Input Register Delays with ZHT Option:
2.0
2.0
2.0
2.0
2.0
2.0
ns
3.0
3.0
3.0
4.0
4.0
4.0
ns
4.0
4.0
4.0
5.0
5.0
6.0 ns
2.0
2.0
2.0
2.0
2.0
2.0 ns
tSIRZ Input register setup time - ZHT
tHIRZ Input register hold time - ZHT
6.0
6.0
6.0
6.0
6.0
6.0
ns
0.0
0.0
0.0
0.0
0.0
0.0
ns
32
MACH 4 Family
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