SPAKMC331MFC20 View Datasheet(PDF) - Motorola => Freescale
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Description
Manufacturer
SPAKMC331MFC20 Datasheet PDF : 254 Pages
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A
Table A-6 16.78 MHz AC Timing
(VDD and VDDSYN = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Num
Characteristic
F1 Frequency of Operation (32.768 kHz crystal)2
Symbol Min
f
0.13
1 Clock Period
tcyc
59.6
1A ECLK Period
1B External Clock Input Period3
tEcyc
tXcyc
476
59.6
2, 3 Clock Pulse Width
tCW
24
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time3
tECW
tXCHL
236
29.8
4, 5 Clock Rise and Fall Time
tCrf
—
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
4B, 5B External Clock Rise and Fall Time4
trf
—
tXCrf
—
6 Clock High to Address, FC, SIZE, RMC Valid
tCHAV
0
7 Clock High to Address, Data, FC, SIZE, RMC High Impedance tCHAZx
0
8 Clock High to Address, FC, SIZE, RMC Invalid
tCHAZn
0
9 Clock Low to AS, DS, CS Asserted
9A AS to DS or CS Asserted (Read)5
tCLSA
2
tSTSA
–15
9C Clock Low to IFETCH, IPIPE Asserted
tCLIA
2
11 Address, FC, SIZE, RMC Valid
to AS, CS Asserted
tAVSA
15
12 Clock Low to AS, DS, CS Negated
12A Clock Low to IFETCH, IPIPE Negated
13 AS, DS, CS Negated to
Address, FC, SIZE Invalid (Address Hold)
tCLSN
2
tCLIN
2
tSNAI
15
14 AS, CS Width Asserted
tSWA
100
14A DS, CS Width Asserted (Write)
tSWAW
45
14B AS, CS Width Asserted (Fast Write Cycle)
15 AS, DS, CS Width Negated6
tSWDW
40
tSN
40
16 Clock High to AS, DS, R/W High Impedance
tCHSZ
—
17 AS, DS, CS Negated to R/W Negated
tSNRN
15
18 Clock High to R/W High
tCHRH
0
20 Clock High to R/W Low
tCHRL
0
21 R/W Asserted to AS, CS Asserted
tRAAA
15
22 R/W Low to DS, CS Asserted (Write)
tRASA
70
23 Clock High to Data Out Valid
tCHDO
—
24 Data Out Valid to Negating Edge of AS, CS
tDVASN
15
25 DS, CS Negated to Data Out Invalid (Data Out Hold)
tSNDOI
15
26 Data Out Valid to DS, CS Asserted (Write)
tDVSA
15
27 Data In Valid to Clock Low (Data Setup)
tDICL
5
27A Late BERR, HALT Asserted to Clock Low (Setup Time)
tBELCL
20
28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN
0
29 DS, CS Negated to Data In Invalid (Data In Hold)7
tSNDI
0
29A DS, CS Negated to Data In High Impedance7, 8
tSHDI
—
30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)7
tCLDI
15
30A CLKOUT Low to Data In High Impedance7
tCLDH
—
31 DSACK[1:0] Asserted to Data In Valid9
tDADI
—
33 Clock Low to BG Asserted/Negated
35 BR Asserted to BG Asserted (RMC Not Asserted)10
tCLBAN
—
tBRAGA
1
37 BGACK Asserted to BG Negated
tGAGN
1
Max
16.78
—
—
—
—
—
—
5
8
5
29
59
—
25
15
22
—
29
22
—
—
—
—
—
59
—
29
29
—
—
29
—
—
—
—
—
80
—
55
—
90
50
29
—
2
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tcyc
tcyc
MOTOROLA
A-8
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
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