Table D-3 SIM Address Map
Access Address 15
87
0
S
$YFFA50
CHIP-SELECT BASE 1 (CSBAR1)
S
$YFFA52
CHIP-SELECT OPTION 1 (CSOR1)
S
$YFFA54
CHIP-SELECT BASE 2 (CSBAR2)
S
$YFFA56
CHIP-SELECT OPTION 2 (CSOR2)
S
$YFFA58
CHIP-SELECT BASE 3 (CSBAR3)
S
$YFFA5A
CHIP-SELECT OPTION 3 (CSOR3)
S
$YFFA5C
CHIP-SELECT BASE 4 (CSBAR4)
S
$YFFA5E
CHIP-SELECT OPTION 4 (CSOR4)
S
$YFFA60
CHIP-SELECT BASE 5 (CSBAR5)
S
$YFFA62
CHIP-SELECT OPTION 5 (CSOR5)
S
$YFFA64
CHIP-SELECT BASE 6 (CSBAR6)
S
$YFFA66
CHIP-SELECT OPTION 6 (CSOR6)
S
$YFFA68
CHIP-SELECT BASE 7 (CSBAR7)
S
$YFFA6A
CHIP-SELECT OPTION 7 (CSOR7)
S
$YFFA6C
CHIP-SELECT BASE 8 (CSBAR8)
D
S
$YFFA6E
S
$YFFA70
S
$YFFA72
S
$YFFA74
CHIP-SELECT OPTION 8 (CSOR8)
CHIP-SELECT BASE 9 (CSBAR9)
CHIP-SELECT OPTION 9 (CSOR9)
CHIP-SELECT BASE 10 (CSBAR10)
S
$YFFA76
CHIP-SELECT OPTION 10 (CSOR10)
$YFFA78
NOT USED
NOT USED
$YFFA7A
NOT USED
NOT USED
$YFFA7C
NOT USED
NOT USED
$YFFA7E
NOT USED
NOT USED
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR
D.3.1 SIMCR — Module Configuration Register
$YFFA00
15
14
13
12
11
10
9
8
7
6
5
EXOFF FRZSW FRZBM 0 SLVEN 0
SHEN
SUPV MM
0
RESET:
0
0
0
0 DATA11 0
0
0
1
1
0
4
3
0
0
IARB
0
111
1
SIMCR controls system configuration. SIMCR can be read or written at any time, ex-
cept for the module mapping (MM) bit, which can only be written once.
EXOFF — External Clock Off
0 = The CLKOUT pin is driven from an internal clock source.
1 = The CLKOUT pin is placed in a high-impedance state.
FRZSW — Freeze Software Enable
0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
counters continue to run.
1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer
counters are disabled, preventing interrupts during software debug.
MOTOROLA
D-14
REGISTER SUMMARY
MC68331
USER’S MANUAL