SPAKMC331MFC20 View Datasheet(PDF) - Motorola => Freescale
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SPAKMC331MFC20 Datasheet PDF : 254 Pages
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D.4 Queued Serial Module
Table D-13 displays the QSM address map. The column labeled “Access” indicates
the privilege level at which the CPU must be operating to access the register. A des-
ignation of “S” indicates that supervisor access is required: a designation of “S/U” in-
dicates that the register can be programmed to the desired privilege level.
Table D-13 QSM Address Map
Access
S
S
S
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
QUEUE RAM
S/U
QUEUE RAM
S/U
QUEUE RAM
Address
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFC1A
$YFFC1C
$YFFC1E
$YFFC20–
$YFFCFF
$YFFD00–
$YFFD1F
$YFFD20–
$YFFD3F
$YFFD40–
$YFFD4F
15
87
0
QSM MODULE CONFIGURATION (QSMCR)
QSM TEST (QTEST)
QSM INTERRUPT LEVEL (QILR) QSM INTERRUPT VECTOR (QIVR)
NOT USED
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SCI STATUS (SCSR)
SCI DATA (SCDR)
NOT USED
NOT USED
NOT USED
PQS DATA (PORTQS)
PQS PIN ASSIGNMENT (PQSPAR) PQS DATA DIRECTION (DDRQS)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
SPI CONTROL 3 (SPCR3)
SPI STATUS (SPSR)
NOT USED
RECEIVE RAM (RR[0:F])
TRANSMIT RAM (TR[0:F])
COMMAND RAM (CR[0:F])
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
D
D.4.1 QSMCR — QSM Configuration Register
$YFFC00
15
14
13
12
11
10
9
8
7
6
5
4
3
0
STOP FRZ1 FRZ0 0
0
0
0
0 SUPV 0
0
0
IARB
RESET:
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
QSMCR bits enable stop and freeze modes, and determine the arbitration priority of
QSM interrupt requests.
STOP — Stop Enable
0 = Normal QSM clock operation
1 = QSM clock operation stopped
When STOP is set, the QSM enters low-power stop mode. System clock input to the
module is disabled. While STOP is asserted, only QSMCR reads are guaranteed to be
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-25
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