Table D-18 Register Bit and Field Mnemonics, (Continued)
Mnemonic
STSIM
SUPV
SW
SWE
SWP
SWT[1:0]
SYS
T[1:0]
TC
TCIE
TDRE
TE
TIE
TOF
TOI
TR[0:F]
TST
V
W
WAKE
WOMQ
WOMS
WREN
WRTO
X
X
Y[5:0]
Z
Name
Stop Mode System Integration Clock
Supervisor/Unrestricted
Software Watchdog Reset
Software Watchdog Enable
Software Watchdog Prescale
Software Watchdog Timing
System Reset
Trace Enable
Transmit Complete
Transmit Complete Interrupt Enable
Transmit Data Register Empty
Transmitter Enable
Transmit Interrupt Enable
Timer Overflow Flag
Timer Overflow Interrupt Enable
Transmit Data RAM
Test Submodule Reset
Overflow Flag
Frequency Control (VCO)
Wakeup by Address Mark
Wired-OR Mode for QSPI Pins
Wired-OR Mode for SCI Pins
Wrap Enable
Wrap To
Extend
Frequency Control Bit (Prescale)
Frequency Control (Counter)
Zero Flag
Register Location
SYNCR
GPTMCR, QSMCR, SIMCR
RSR
SYPCR
SYPCR
SYPCR
RSR
SR
SCSR
SCCR1
SCSR
SCCR1
SCCR1
TFLG2
TMSK2
QSPI RAM
RSR
CCR
SYNCR
SCCR1
SPCR0
SCCR1
SPCR2
SPCR2
CCR
SYNCR
SYNCR
CCR
D
MC68331
USER’S MANUAL
REGISTER SUMMARY
MOTOROLA
D-43