SPAKMC331MFC20 View Datasheet(PDF) - Motorola => Freescale
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SPAKMC331MFC20 Datasheet PDF : 254 Pages
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4
Both writes must occur before time-out in the order listed, but any number of instruc-
tions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and soft-
ware watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
Table 4-3 MODCLK Pin and SWP Bit During Reset
MODCLK
0 (External Clock)
1 (Internal Clock)
SWP
1 (÷ 512)
0 (÷ 1)
The SWT field selects the divide ratio used to establish software watchdog time-out
period. Time-out period is given by the following equations.
Time-out Period = E----X----T----A----L-----F----r--e---q---u----e---n-1--c---y-----⁄--D-----i-v---i-d----e-----R----a---t--i-o--
or
Time-out Period = E----X----T-D---A-i-v--L-i--d--F-e---r--eR---q-a--u--t-i-e-o--n---c---y--
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new time-
out period can take effect.
Table 4-4 Software Watchdog Ratio
SWP
0
0
0
0
1
1
1
1
SWT
00
01
10
11
00
01
10
11
Ratio
29
211
213
215
218
220
222
224
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
MOTOROLA
4-6
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
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