SPAKMC331MFC20 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
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SPAKMC331MFC20 Datasheet PDF : 254 Pages
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4
Table 4-18 SIM Pin Reset States
Mnemonic
CS10/ADDR23
CS[9:6]/ADDR[22:19]/PC[6:3]
ADDR[18:0]
AS/PE5
AVEC/PE2
BERR
CSM/BG
CSE/BGACK
CS0/BR
CLKOUT
CSBOOT
DATA[15:0]
DS/PE4
DSACK0/PE0
DSACK1/PE1
CS5/FC2/PC2
FC1/PC1
CS3/FC0/PC0
HALT
IRQ[7:1]/PF[7:1]
MODCLK/PF0
R/W
RESET
RMC
SIZ[1:0]/PE[7:6]
TSC
State While
RESET
Asserted
1
1
High-Z Output
High-Z Output
Disabled
Disabled
1
1
1
Output
1
Mode Select
Disabled
Disabled
Disabled
1
1
1
Disabled
Disabled
Mode Select
Disabled
Asserted
Disabled
Disabled
Mode Select
Pin State After RESET Released
Pin
Pin State
Pin
Pin State
Function
Function
CS10
1
ADDR23 Unknown
CS[9:6]
1
ADDR[22:19] Unknown
ADDR[18:0] Unknown ADDR[18:0] Unknown
AS
Output
PE5
Input
AVEC
Input
PE2
Input
BERR
Input
BERR
Input
CSM
1
BG
1
CSE
1
BGACK
Input
CS0
1
BR
Input
CLKOUT
Output
CLKOUT
Output
CSBOOT
0
CSBOOT
0
DATA[15:0]
Input
DATA[15:0]
Input
DS
Output
PE4
Input
DSACK0
Input
PE0
Input
DSACK1
Input
PE1
Input
CS5
1
FC2
Unknown
FC1
1
FC1
Unknown
CS3
1
FC0
Unknown
HALT
Input
HALT
Input
IRQ[7:1]
Input
PF[7:1]
Input
MODCLK
Input
PF0
Input
R/W
Output
R/W
Output
RESET
Input
RESET
Input
RMC
Output
PE3
Input
SIZ[1:0]
Unknown
PE[7:6]
Input
TSC
Input
TSC
Input
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules
As a rule, module pins that are assigned to general-purpose I/O ports go to active high-
impedance state following reset. Other pin states are determined by individual module
control register settings. Refer to sections concerning modules for details. However,
during power-up reset, module port pins may be in an indeterminate state for a short
period. Refer to 4.6.7 Power-On Reset for more information.
4.6.6 Reset Timing
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven, to guarantee this length of reset to the entire system.
MOTOROLA
4-42
SYSTEM INTEGRATION MODULE
MC68331
USER’S MANUAL
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