M29W640DB90N6T(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M29W640DB90N6T
(Rev.:2004)

64 Mbit (8Mb x8 or 4Mb x16, Boot Block) 3V Supply Flash Memory

STMicroelectronics 

M29W640DT, M29W640DB

REVISION HISTORY

Table 29. Document Revision History

Date

Version

Revision Details

14-Dec-2001

-01

Document released

Description of Ready/Busy signal clarified (and Figure 12. modified)

19-Apr-2002

-02

Clarified allowable commands during Block Erase

Clarified the mode the device returns to in the CFI Read Query command section

tPLYH (time to reset device) respecified. Correction to table of Commands.

24-Apr-2002

-03

Values for addresses 23h and 25h corrected in CFI Query System Interface Information

table in Appendix B

When in Extended Block mode, the block at the boot block address can be used as OTP.

Value of electronic signature changed. Data Toggle Flow chart corrected. SO44 package

05-Sep-2002

3.1

removed. Double Word Program Time (typ) changed to 20s. Revision numbering

modified: a minor revision will be indicated by incrementing the digit after the dot, and a

major revision, by incrementing the digit before the dot (revision version 03 equals 3.0).

08-Jan-2003

Values corrected for typical times for Double Word Program (Byte or Word) and Chip

3.2

Program (Quadruple Byte, Double Word) in the Program, Erase Times and Program,

Erase Endurance Cycles table.

Document promoted from Product Preview to Preliminary Data.

04-Apr-2003

Data Retention and Erase Suspend Latency Time parameters added to Table

6., Program, Erase Times and Program, Erase Endurance Cycles, and Typical after 100k

W/E Cycles column removed.

IID (Identification) current removed from Table 11., DC Characteristics. Data modified at

addresses 2Eh, 31h, 32h in Table 24.

Extended Memory Block Verify Codes modified in Tables 2 and 3, “Bus Operations, BYTE

3.3

= VIL” and “Bus Operations, BYTE = VIH”, respectively. Block 75 address space corrected

for x8 mode in Table 19., Top Boot Block Addresses, M29W640DT, and Block 71

address space corrected for x8 mode in Table 20., Bottom Boot Block Addresses,

M29W640DB.

APPENDIX C., EXTENDED MEMORY BLOCK, added. VSS pin connection to ground

clarified.

Lead-free package options E and F added to Table 18., Ordering Information Scheme.

2-Oct-2003

Status of Ready/Busy signal for Erase Suspend Operation modified in Table 7, Status

Register Bits.

Double Word Program Command modified in COMMAND INTERFACE section.

3.4

TLEAD parameter added in Table 8., Absolute Maximum Ratings.

Note modified and addresses 31h to 3Ch added in Table 24., Device Geometry

Definition.

Addresses 43h and 4Eh modified; addresses 4Fh and 50h added in Table 25., Primary

Algorithm-Specific Extended Query Table.

10-Nov-2003

3.5

70ns access time option removed.

VPP and IPP test conditions updated in Table 11., DC Characteristics.

Block Protect/Unprotect code updated in APPENDIX B., Table 25..

Customer Lockable Extended Block mechanism modified in APPENDIX C., EXTENDED

19-Dec-2003

3.6

MEMORY BLOCK.

APPENDIX D., BLOCK PROTECTION updated: Note 1 added in the In-System

Technique section and Note 2 added below Figure 18., In-System Equipment Group

Protect Flowchart.

Document status updated to Full Datasheet.

10-Dec-2004

5.0

Status of Ready/Busy signal for Program Error, Chip Erase and Block Erase modified in

Table 7., Status Register Bits.

48/49

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