MC9S08SH8CSC View Datasheet(PDF) - Freescale Semiconductor
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MC9S08SH8CSC Datasheet PDF : 341 Pages
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Chapter 11 Inter-Integrated Circuit (S08IICV2)
11.3.3 IIC Control Register (IICC1)
7
6
5
4
3
2
1
0
R
0
0
0
IICEN
IICIE
MST
TX
TXAK
W
RSTA
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-5. IIC Control Register (IICC1)
Table 11-6. IICC1 Field Descriptions
Field
7
IICEN
6
IICIE
5
MST
4
TX
3
TXAK
2
RSTA
Description
IIC Enable. The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled
1 IIC is enabled
IIC Interrupt Enable. The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled
1 IIC interrupt request enabled
Master Mode Select. The MST bit changes from a 0 to a 1 when a start signal is generated on the bus and
master mode is selected. When this bit changes from a 1 to a 0 a stop signal is generated and the mode of
operation changes from master to slave.
0 Slave mode
1 Master mode
Transmit Mode Select. The TX bit selects the direction of master and slave transfers. In master mode, this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit is always high.
When addressed as a slave, this bit should be set by software according to the SRW bit in the status register.
0 Receive
1 Transmit
Transmit Acknowledge Enable. This bit specifies the value driven onto the SDA during data acknowledge
cycles for master and slave receivers.
0 An acknowledge signal is sent out to the bus after receiving one data byte
1 No acknowledge signal response is sent
Repeat start. Writing a 1 to this bit generates a repeated start condition provided it is the current master. This
bit is always read as cleared. Attempting a repeat at the wrong time results in loss of arbitration.
MC9S08SH8 MCU Series Data Sheet, Rev. 3
170
Freescale Semiconductor
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