TS68230 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TS68230

HMOS PARALLEL INTERFACE/TIMER

STMicroelectronics 

TS68230

of chip select, then three-stated to avoid interfe-

rence with the next bus cycle.

The system designer must take care that DTACK is

negated and three-stated quickly enough after each

bus cycle to avoid interference with the next one.

With an TS68000 this necessitates a relatively fast

external path from the data strobe negation to CS

bus master negation.

1.4.2. INTERRUPT ACKNOWLEDGE CYCLES.

Special internal operations take place on PI/T inter-

rupt acknowledge cycles. The port interrupt vector

register or the timer vector register are implicitly ad-

dressed by the assertion of PC6/PIACK or

PC7/TIACK, respectively. The signals are first syn-

chronized with the falling edge of the clock. One

clock period after they are recognized, the data bus

buffers are enabled and the vector is driven onto the

bus. DTACK is asserted after another clock period

to allow the vector some setup time prior to DTACK.

DTACK is negated, then three-stated, as with nor-

mal read or write cycles, when PIACK or TIACK is

negated.

1.4.3. WRITE CYCLES. In many ways, write cycles

are similar to normal read cycles. On write cycles,

data at the D0-D7 pins must meet the same setup

specifications as the register select and R/W lines.

Like these signals, write data is latched on the as-

serted edge of CS, and must meet small setup and

hold time requirements with respect to that edge.

The same bus cycle recovery conditions exist as for

normal read cycles. No other differences exist.

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