TS68230 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

TS68230

HMOS PARALLEL INTERFACE/TIMER

STMicroelectronics 

TS68230

Figure 5.3 : Single Interrupt after Timeout Example.

5.2.4. ELAPSED TIME MEASUREMENT EXAM-

PLES. Elapsed time measurement takes several

forms ; two forms are described in the following

paragraphs.

5.2.4.1. System Clock Example.

76 5 4 32 1 0

TOUT/TIACK

Control

Z.D

Control

*

Clock

Control

Timer

Enable

0 0 X 1 0 0 0 Changed

This configuration allows time interval measure-

ment by software. The TIN pin may be used as an

external timer enable if desired.

Figure 5.4 : Elapsed Time Measurement Example.

The processor loads the counter preload registers

(generally with all ones), loads the timer control re-

gister, and then enables the timer. The counter is al-

lowed to decrement until the ending event takes

place. When it is desired to read the time interval, the

processor must halt the timer and then read the

counter. If TIN is used as an enable, the start and

stop counter functions are controlled externally.

For applications in which the interval may exceed

the programmed time interval, zero detection can be

counted by polling the status register or through in-

terrupts to simulate additional timer bits. Note that

the ZDS bit is latched and should be cleared after

each detection of zero. At the end, the timer can be

halted and read (see figure 5.4).

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