PSD953F2-70UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD953F2-70UI

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Table 20. Port Operating Mode Settings

Mode

Defined in

PSDabel

Defined in PSD

Configuration

Control Direction

Register Register

Setting Setting

VM

Register

Setting

JTAG Enable

MCU I/O

Declare pins only N/A1

1 = output,

0

0 = input N/A

N/A

(Note 2)

PLD I/O

Logic equations N/A

N/A

(Note 2) N/A

N/A

Data Port (Port A) N/A

Specify bus type N/A

N/A

N/A

N/A

Address Out

(Port A,B)

Declare pins only N/A

1

1 (Note 2) N/A

N/A

Address In

(Port A,B,C,D)

Logic for equation

Input Macrocells

N/A

N/A

N/A

N/A

N/A

Peripheral I/O

(Port A)

Logic equations

(PSEL0 & 1)

N/A

N/A

N/A

PIO bit = 1 N/A

JTAG ISP (Note 3) JTAGSEL

JTAG

Configuration

N/A

N/A

N/A

JTAG_Enable

Note: 1. N/A = Not Applicable

2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product

term (.oe) from the CPLD AND Array.

3. Any of these three methods enables the JTAG pins on Port C.

Table 21. I/O Port Latched Address Output Assignments

MCU

Port A (PA3-PA0) Port A (PA7-PA4)

8051XA (8-Bit)

N/A1

Address a7-a4

80C251

(Page Mode)

N/A

N/A

All Other

8-Bit Multiplexed

Address a3-a0

Address a7-a4

8-Bit

Non-Multiplexed Bus

N/A

N/A

Note: 1. N/A = Not Applicable.

Port B (PB3-PB0)

Address a11-a8

Address a11-a8

Address a3-a0

Address a3-a0

Port B (PB7-PB4)

N/A

Address a15-a12

Address a7-a4

Address a7-a4

54/110

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