PSD913F2V-70UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD913F2V-70UI

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Automatic Power-down (APD) Unit and Power-down Mode

The APD Unit, shown in Figure 32, puts the PSD

into Power-down mode by monitoring the activity

of Address Strobe (ALE/AS, PD0). If the APD Unit

is enabled, as soon as activity on Address Strobe

(ALE/AS, PD0) stops, a four bit counter starts

counting. If Address Strobe (ALE/AS, PD0) re-

mains inactive for fifteen clock periods of CLKIN

(PD1), Power-down (PDN) goes High, and the

PSD enters Power-down mode, as discussed

next.

Power-down Mode. By default, if you enable the

APD Unit, Power-down mode is automatically en-

abled. The device enters Power-down mode if Ad-

dress Strobe (ALE/AS, PD0) remains inactive for

fifteen periods of CLKIN (PD1).

The following should be kept in mind when the

PSD is in Power-down mode:

registers. The blocked signals include MCU

control signals and the common CLKIN (PD1).

Note that blocking CLKIN (PD1) from the

PLDs does not block CLKIN (PD1) from the

APD Unit.

– All PSD memories enter Standby mode and

are drawing standby current. However, the

PLD and I/O ports blocks do not go into

Standby Mode because you don’t want to

have to wait for the logic and I/O to “wake-up”

before their outputs can change. See Table 28

for Power-down mode effects on PSD ports.

– Typical standby current is of the order of

microamperes. These standby current values

assume that there are no transitions on any

PLD input.

– If Address Strobe (ALE/AS, PD0) starts

pulsing again, the PSD returns to normal

Operating mode. The PSD also returns to

normal Operating mode if either PSD Chip

Select Input (CSI, PD2) is Low or the Reset

(RESET) input is High.

Table 28. Power-down Mode’s Effect on Ports

Port Function

Pin Level

MCU I/O

No Change

PLD Out

No Change

– The MCU address/data bus is blocked from all

memory and PLDs.

– Various signals can be blocked (prior to

Power-down mode) from entering the PLDs by

setting the appropriate bits in the PMMR

Address Out

Data Port

Peripheral I/O

Undefined

Tri-State

Tri-State

Figure 32. APD Unit

APD EN

PMMR0 BIT 1=1

TRANSITION

DETECTION

ALE

RESET

CSI

CLKIN

EDGE

DETECT

CLR PD

APD

COUNTER

PD

DISABLE BUS

INTERFACE

EEPROM SELECT

FLASH SELECT

PLD SRAM SELECT

POWER DOWN

(PDN) SELECT

DISABLE

FLASH/EEPROM/SRAM

AI02891

Table 29. PSD Timing and Stand-by Current during Power-down Mode

Mode

PLD Propagation

Delay

Memory

Access Recovery Time

Access Time

to Normal Access

Typical Stand-by Current

5V VCC

3V VCC

Power-down Normal tPD (Note 1)

No Access

tLVDV

75µA (Note 2) 25µA (Note 2)

Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit.

2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo Bit is ’0.’

63/110

Share Link: