PSD954F5-70UIT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD954F5-70UIT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 52. CPLD Macrocell Asynchronous Clock Mode Timing (3V devices)
Symbol Parameter
Conditions
-12
Min Max
-15
Min Max
-20
Min Max
PT Turbo Slew
Aloc Off Rate
Unit
Maximum
Frequency
External
Feedback
1/(tSA+tCOA)
21.7
19.2
16.9
MHz
fMAXA
Maximum
Frequency
Internal
Feedback
(fCNTA)
1/(tSA+tCOA–10)
27.8
23.8
20.4
MHz
Maximum
Frequency
1/(tCHA+tCLA)
33.3
27
24.4
Pipelined Data
MHz
tSA
Input Setup
Time
10
12
13
+ 4 + 20
ns
tHA
Input Hold Time
12
15
17
ns
tCHA
Clock High Time
17
22
25
+ 20
ns
tCLA
Clock Low Time
13
15
16
+ 20
ns
tCOA
Clock to Output
Delay
36
40
46
+ 20 – 6 ns
tARD
CPLD Array
Delay
Any macrocell
25
29
33 + 4
ns
tMINA
Minimum Clock
Period
1/fCNTA
36
42
49
ns
85/110
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