PSD853F5A-70UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD853F5A-70UI Datasheet PDF : 128 Pages
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PSD architectural overview
PSD8XXFX
The PSD also has some bits that are configured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches
its outputs and goes to sleep until the next transition on its inputs.
Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD
to reduce power consumption. Please see Section 17: Power management for more details.
Table 5.
PC0
PC1
PC3
PC4
PC5
PC6
JTAG SIgnals on port C
Port C pins
TMS
TCK
TSTAT
TERR
TDI
TDO
JTAG signal
Table 6. Methods for programming different functional blocks of the PSD
Functional block
JTAG
programming
Device
programmer
IAP
Primary Flash memory
Yes
Yes
Yes
Secondary Flash memory
Yes
Yes
Yes
PLD array (DPLD and CPLD)
Yes
Yes
No
PSD configuration
Yes
Yes
No
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Doc ID 7833 Rev 7
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