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PSD853F5A-70UI View Datasheet(PDF) - STMicroelectronics

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PSD853F5A-70UI Datasheet PDF : 128 Pages
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PSD8XXFX
Figure 6. Data Polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
Programming Flash memory
DQ7
=
YES
DATA
NO
NO DQ5
=1
YES
READ DQ7
DQ7
=
YES
DATA
NO
FAIL
PASS
AI01369B
8.2
Data Toggle
Checking the Toggle flag bit (DQ6) is a method of determining whether a program or erase
cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm.
When the MCU issues a Program instruction, the embedded algorithm within the PSD
begins. The MCU then reads the location of the byte to be programmed in Flash memory to
check status. The Toggle flag bit (DQ6) of this location toggles each time the MCU reads
this location until the embedded algorithm is complete. The MCU continues to read this
location, checking the Toggle flag bit (DQ6) and monitoring the Error flag bit (DQ5). When
the Toggle flag bit (DQ6) stops toggling (two consecutive reads yield the same value), and
the Error flag bit (DQ5) remains ’0,’ the embedded algorithm is complete. If the Error flag bit
(DQ5) is '1,' the MCU should test the Toggle flag bit (DQ6) again, since the Toggle flag bit
(DQ6) may have changed simultaneously with the Error flag bit (DQ5, see Figure 7).
The Error flag bit (DQ5) is set if either an internal timeout occurred while the embedded
algorithm attempted to program the byte, or if the MCU attempted to program a '1' to a bit
that was not erased (not erased is logic '0').
It is suggested (as with all Flash memories) to read the location again after the embedded
programming algorithm has completed, to compare the byte that was written to Flash
memory with the byte that was intended to be written.
When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle
flag bit (DQ6) toggles until the Erase cycle is complete. A '1' on the Error flag bit (DQ5)
indicates a timeout condition on the Erase cycle; a '0' indicates no error. The MCU can read
Doc ID 7833 Rev 7
35/128

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