PSD853F5VA-70UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD853F5VA-70UI

Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

STMicroelectronics 

PSD8XXFX

Specific features

10.3

Reset (RESET) signal (on the PSD83xF2 and PSD85xF2)

A pulse on Reset (RESET) aborts any cycle that is in progress, and resets the Flash

memory to the READ mode. When the reset occurs during a program or erase cycle, the

Flash memory takes up to 25μs to return to the READ mode. It is recommended that the

Reset (RESET) pulse (except for Power On Reset, as described in Section 18: Reset timing

and device status at reset) be at least 25 µs so that the Flash memory is always ready for

the MCU to fetch the bootstrap instructions after the Reset cycle is complete.

Table 12. Sector Protection/Security Bit definition – Flash Protection register(1)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

1. Bit Definitions:

Sec<i>_Prot 1 = Primary Flash memory or secondary Flash memory Sector <i> is write protected.

Sec<i>_Prot 0 = Primary Flash memory or secondary Flash memory Sector <i> is not write protected.

Table 13. Sector Protection/Security Bit definition – PSD/EE Protection register(1)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Security_B

it

not used

not used

not used

Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

1. Bit Definitions:

Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.

Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.

Security_Bit 0 = Security Bit in device has not been set.

1 = Security Bit in device has been set.

Doc ID 7833 Rev 7

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