PSD853F3VA-12UIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD853F3VA-12UIT

Flash in-system programmable (ISP) peripherals for 8-bit MCUs, 5 V

STMicroelectronics 

Page register

13 Page register

PSD8XXFX

The 8-bit Page register increases the addressing capability of the MCU by a factor of up to

256. The contents of the register can also be read by the MCU. The outputs of the Page

register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector

Select (FS0-FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations.

If memory paging is not needed, or if not all 8 page register bits are needed for memory

paging, then these bits may be used in the CPLD for general logic. See Application Note

AN1154.

Figure 11 shows the Page register. The eight flip-flops in the register are connected to the

internal data bus D0-D7. The MCU can write to or read from the Page register. The Page

register can be accessed at address location CSIOP + E0h.

Figure 11. Page register

RESET

D0

Q0

D1

Q1

D0-D7 D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

R/W

D7

Q7

PAGE

REGISTER

PGR0

PGR1

PGR2

PGR3

PGR4

PGR5

PGR6

PGR7

DPLD

AND

CPLD

PLD

INTERNAL

SELECTS

AND LOGIC

AI02871B

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Doc ID 7833 Rev 7

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