PSD8532V-70UIT View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD8532V-70UIT Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
80C51XA
The Philips 80C51XA MCU family supports an 8-
or 16-bit multiplexed bus that can have burst cy-
cles. Address bits (A3-A0) are not multiplexed,
while (A19-A4) are multiplexed with data bits
(D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4)
are multiplexed with data bits (D7-D0).
The 80C51XA can be configured to operate in
eight-bit data mode (as shown in Figure 24).
The 80C51XA improves bus throughput and per-
formance by executing burst cycles for code fetch-
es. In Burst Mode, address A19-A4 are latched
internally by the PSD, while the 80C51XA changes
the A3-A0 signals to fetch up to 16 bytes of code.
The PSD access time is then measured from ad-
dress A3-A0 valid to data in valid. The PSD bus
timing requirement in Burst Mode is identical to the
normal bus cycle, except the address setup and
hold time with respect to Address Strobe (ALE/AS,
PD0) does not apply.
Figure 24. Interfacing the PSD with the 80C51X, 8-bit Data Bus
RESET
80C51XA
21
20
XTAL1
XTAL2
11 RXD0
13
6
7
TXD0
RXD1
TXD1
9
8
T2EX
T2
16 T0
10 RST
14 INT0
15
INT1
A0/WRH
A1
A2
2
3
4
A3 5
A4D0
A5D1
A6D2
A7D3
43
42
41
40
39
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
38
37
36
24
25
26
27
A15D11
A16D12
28
A17D13
A18D14
29
30
31
A19D15
A0
A1
A2
A3
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12
A13
A14
A15
A16
A17
A18
A19
35 EA/WAIT
17 BUSW
PSEN 32
RD 19
WRL 18
33
ALE
PSEN
RD
WR
ALE
RESET
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
PSD
30
31 ADIO0
32
33
ADIO1
ADIO2
ADIO3
34
35
AD104
AD105
36
37
ADIO6
ADIO7
A12
A13
39
40
ADIO8
A14
A15
A16
A17
A18
A19
41
42
43
44
45
46
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
47 CNTL0 (WR)
50 CNTL1(RD)
49 CNTL 2(PSEN)
10
8 PD0-ALE
9
PD1
PD2
48
RESET
29 A0
PA0
PA1
28
A1
PA2 27 A2
PA3
PA4
PA5
25
24
23
A3
PA6 22
PA7 21
7
PB0
PB1
PB2
PB3
6
5
4
PB4
3
2
PB5
PB6
PB7
52
51
20
PC0
PC1
PC2
PC3
PC4
19
18
17
14
PC5
PC6
PC7
13
12
11
AI02883C
49/110
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