PSD8145-12UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD8145-12UI Datasheet PDF : 110 Pages
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Figure 41. Synchronous Clock Mode Timing – PLD
tCH
tCL
CLKIN
INPUT
REGISTERED
OUTPUT
tS
tH
tCO
AI02860
Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
Fast
PT
Aloc
Turbo
Off
Slew
rate1
Unit
Maximum
Frequency
External
Feedback
1/(tS+tCO)
40.0
30.30
25.00
MHz
fMAX
Maximum
Frequency
Internal
Feedback
(fCNT)
1/(tS+tCO–10)
66.6
43.48
31.25
MHz
Maximum
Frequency
Pipelined Data
1/(tCH+tCL)
83.3
50.00
35.71
MHz
tS
Input Setup
Time
12
15
20
+ 2 + 10
ns
tH
Input Hold Time
0
0
0
ns
tCH
Clock High Time Clock Input 6
10
15
ns
tCL
Clock Low Time Clock Input 6
10
15
ns
tCO
Clock to Output
Delay
Clock Input
13
18
22
– 2 ns
tARD
CPLD Array
Delay
Any macrocell
11
16
22 + 2
ns
tMIN
Minimum Clock
Period 2
tCH+tCL
12
20
30
ns
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2. CLKIN (PD1) tCLCL = tCH + tCL.
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