SI3019-F-FM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

Manufacturer

SI3019-F-FM

PROGRAMMABLE VOICE DAA SOLUTIONS

Silicon Laboratories 

Si3050 + Si3011/18/19

Table 8. Switching Characteristics—PCM Highway Serial Interface

(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)

Parameter1

Symbol

Test

Conditions

Min

Typ

Max Units

Cycle Time PCLK

tp

122

—

3906

ns

Valid PCLK Inputs

—

256

—

kHz

—

512

—

kHz

—

768

—

kHz

—

1.024

—

MHz

—

1.536

—

MHz

—

2.048

—

MHz

—

4.096

—

MHz

—

8.192

—

MHz

FSYNC Period2

tfp

—

125

—

s

PCLK Duty Cycle

tdty

40

50

60

%

PCLK Jitter-Tolerance

tjitter

—

—

2

ns

FSYNC Jitter Tolerance

tjitter

—

—

±120

ns

Rise Time, PCLK

tr

—

—

25

ns

Fall Time, PCLK

tf

—

—

25

ns

Delay Time, PCLK Rise to DTX Active

td1

—

—

20

ns

Delay Time, PCLK Rise to DTX Transition

td2

Delay Time, PCLK Rise to DTX Tri-State3

td3

—

—

20

ns

—

—

20

ns

Setup Time, FSYNC Rise to PCLK Fall

tsu1

25

—

—

ns

Hold Time, PCLK Fall to FSYNC Fall

th1

20

—

—

ns

Setup Time, DRX Transition to PCLK Fall

tsu2

25

—

—

ns

Hold Time, PCLK Falling to DRX Transition

th2

20

—

—

ns

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO – 0.4 V, VIL = 0.4 V, rise and fall

times are referenced to the 20% and 80% levels of the waveform.

2. FSYNC must be 8 kHz under all operating conditions.

3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.

PCLK

tsu1

FSYNC

tp

th1

t fp

DRX

tsu2

th2

td1

td2

td3

DTX

Figure 4. PCM Highway Interface Timing Diagram (RXS = TXS = 1)

12

Rev. 1.5

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