M48T128YPM(2010) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48T128YPM Datasheet PDF : 23 Pages
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Operation modes
M48T128Y, M48T128V
Table 4. WRITE mode AC characteristics
Symbol
Parameter(1)
M48T128Y
–70
M48T128V
–85
Unit
Min Max Min Max
tAVAV WRITE cycle time
70
85
ns
tAVWL Address valid to WRITE enable low
0
0
ns
tAVEL Address valid to chip enable low
0
0
ns
tWLWH WRITE enable pulse width
50
60
ns
tELEH Chip enable low to chip enable 1 high
55
65
ns
tWHAX WRITE enable high to address transition
5
5
ns
tEHAX Chip enable high to address transition
10
15
ns
tDVWH Input valid to WRITE enable high
30
35
ns
tDVEH Input valid to chip enable high
30
35
ns
tWHDX WRITE enable high to input transition
5
5
ns
tEHDX Chip enable high to input transition
tWLQZ(2)(3) WRITE enable low to output Hi-Z
10
15
ns
25
30
ns
tAVWH Address valid to WRITE enable high
60
70
ns
tAVEH Address valid to chip enable high
60
tWHQX(2)(3) WRITE enable high to output transition
5
70
ns
5
ns
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Note:
Data retention mode
With valid VCC applied, the M48T128Y/V operates as a conventional BYTEWIDEâ„¢ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “Don't care.â€
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T128Y/V may respond to transient noise spikes on VCC that
reach into the deselect window during the time the device is sampling VCC. Therefore,
decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit switches power to the internal battery,
preserving data and powering the clock. The internal energy source will maintain data in the
M48T128Y/V for an accumulated period of at least 10 years at room temperature. As
system power rises above VSO, the battery is disconnected, and the power supply is
switched to external VCC. Deselect continues for tREC after VCC reaches VPFD (max).
10/23
Doc ID 5746 Rev 6
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