M48T128VPM(2010) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48T128VPM Datasheet PDF : 23 Pages
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Clock operations
M48T128Y, M48T128V
Table 5. Register map
Data
Address
D7 D6 D5 D4 D3 D2 D1 D0
1FFFFh
1FFFEh 0
1FFFDh 0
1FFFCh 0
1FFFBh 0
1FFFAh 0
1FFF9h ST
1FFF8h W
10 years
0
0 10 M
0
10 date
FT 0
0
0
10 hours
10 minutes
10 seconds
R
S
Year
Month
Date
0
Day
Hours
Minutes
Seconds
Calibration
Keys:
S = SIGN bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
Function/range
BCD format
Year
Month
Date
Day
Hours
Minutes
Seconds
Control
00-99
01-12
01-31
01-07
00-23
00-59
00-59
3.4
Calibrating the clock
The M48T128Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which
equates to about ±1.53 minutes per month. When the Calibration circuit is properly
employed, accuracy improves to better than +1/–2 ppm at 25 °C. The oscillation rate of
crystals changes with temperature (see Figure 7 on page 13). The M48T128Y/V design
employs periodic counter correction. The calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 128 stage, as shown in Figure 8 on page 13.
The number of times pulses are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
control register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the control register
1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120
actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in
the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of
the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75 minutes per month.
12/23
Doc ID 5746 Rev 6
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