ST92F150CV1TBE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F150CV1TBE

8/16-bit single voltage Flash MCU family with RAM, E³ ™ (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto

4

I/O ports

I/O ports

Port 0, Port 1 and Port 9[7:2] provide the external memory interface. All the ports of the

device can be programmed as Input/Output or in Input mode, compatible with TTL or CMOS

levels (except where Schmitt Trigger is present). Each bit can be programmed individually

(Refer to Section 13: I/O ports.

Internal weak pull-up

As shown in Table 5, not all input sections implement a Weak Pull-up. This means that the

pull-up must be connected externally when the pin is not used or programmed as

bidirectional.

TTL/CMOS input

For all those port bits where no input schmitt trigger is implemented, it is always possible to

program the input level as TTL or CMOS compatible by programming the relevant PxC2.n

control bit. Refer to Section 13.4: Input/output bit configuration in Section 13: I/O ports.

Schmitt trigger input

Two different kinds of Schmitt Trigger circuitries are implemented: Standard and High

Hysteresis. Standard Schmitt Trigger is widely used (see Table 5), while the High Hysteresis

Schmitt Trigger is present on ports P4[7:6] and P6[5:4].

All inputs which can be used for detecting interrupt events have been configured with a

“Standard” Schmitt Trigger, apart from the NMI pin which implements the “High Hysteresis”

version. In this way, all interrupt lines are guaranteed as “edge sensitive”.

Push-pull/OD output

The output buffer can be programmed as push-pull or open-drain: attention must be paid to

the fact that the open-drain option corresponds only to a disabling of P-channel MOS

transistor of the buffer itself: it is still present and physically connected to the pin.

Consequently, it is not possible to increase the output voltage on the pin over VDD+0.3 Volt,

to avoid direct junction biasing.

Pure open-drain output

The user can increase the voltage on an I/O pin over VDD+0.3 Volt where the P-channel

MOS transistor is physically absent: this is allowed on all “Pure Open Drain” pins. In this

case, the push-pull option is not available and any weak pull-up must be implemented

externally.

Table 5. I/O port characteristics

Port

Input

Output

Weak pull-up Reset state

Port 0[7:0]

Port 1[7:3]

Port 1[2:0]

Port 2[1:0]

Port 2[3:2]

Port 2[5:4]

Port 2[7:6]

TTL/CMOS

TTL/CMOS

TTL/CMOS

Schmitt trigger

TTL/CMOS

Schmitt trigger

TTL/CMOS

Push-Pull/OD No

Push-Pull/OD Yes

Push-Pull/OD No

Push-Pull/OD Yes

Pure OD

No

Push-Pull/OD Yes

Push-Pull/OD Yes

Bidirectional

Bidirectional

WPU

Bidirectional

Input

Input CMOS

Input

Input CMOS

Doc ID 13898 Rev 2

41/522

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