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ST92F250CV2QBTR View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST92F250CV2QBTR Datasheet PDF : 524 Pages
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ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
Description
The SPI is a synchronous serial interface for Master and Slave device communication. It
supports single master and multimaster systems.
A J1850 Byte Level Protocol Decoder is available (ST92F150JDV1 device only) for
communicating with a J1850 network.
The bxCAN (basic extended) interface (two in the ST92F150JDV1 device) supports 2.0B
Active protocol. It has 3 transmit mailboxes, 2 independent receive FIFOs and 8 filters.
In addition, there is a 16 channel Analog to Digital Converter with integral sample and hold,
fast conversion time and 10-bit resolution.
There is one Multiprotocol Serial Communications Interface with an integral generator,
asynchronous and synchronous capability (fully programmable format) and associated
address/wake-up option, plus two DMA channels.
On 100-pin devices, there is an additional asynchronous Serial Communications interface
with 13-bit LIN Synch Break generation capability.
Finally, a programmable PLL Clock Generator allows the usage of standard 3 to 5 MHz
crystals to obtain a large range of internal frequencies up to 24 MHz. Low power Run
(SLOW), Wait For Interrupt, low power Wait For Interrupt, STOP and HALT modes are also
available.
Doc ID 8848 Rev 7
21/523

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