Pinout and pin description
ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2
Figure 15. ST92F250: Pin configuration (top-view LQFP100)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
A20/P9.6 1
75
A21/P9.7 2
74
TX/WAIT/WKUP5/P5.0 3
73
RX/WKUP6/WDOUT/P5.1 4
72
SIN/WKUP2/P5.2 5
71
WDIN/SOUT/P5.3 6
70
TXCLK/CLKOUT/P5.4 7
69
RXCLK/WKUP7/P5.5 8
68
DCD/WKUP8/P5.6 9
67
WKUP9/RTS/P5.7 10
66
ICAPA1/P4.0 11
65
CLOCK2/P4.1 12
OCMPA1/P4.2 13
ST92F250
64
63
VSS 14
62
VDD 15
61
ICAPB1/OCMPB1/P4.3 16
60
EXTCLK1/WKUP4/P4.4 17
59
EXTRG/STOUT/P4.5 18
58
SDA0/P4.6 19
57
WKUP1/SCL0/P4.7 20
56
ICAPB0/P3.1 21
55
ICAPA0/OCMPA0/P3.2 22
54
OCMPB0/P3.3 23
53
EXTCLK0/SS/P3.4 24
52
MISO/P3.5 25
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P8.4/AIN4
P8.3/AIN3
P8.2/AIN2
P8.1/AIN1/WKUP15
P8.0/AIN0/WKUP14
P3.0
P6.5/WKUP10/INTCLK
P6.4/NMI
P6.3/INT3/INT5
P6.2/INT2/INT4/DS2
P6.1/INT6/RW
P6.0/INT0/INT1/CLOCK2/8
P0.7/A7/D7
VDD
VSS
P0.6/A6/D6
P0.5/A5/D5
P0.4/A4/D4
P0.3/A3/D3
P0.2/A2/D2
P0.1/A1/D1
P0.0/A0/D0
AS
DS
P1.7/A15
* VTEST must be kept low in standard operating mode.
Table 3.
Name
VDD
VSS
AVDD
AVSS
VTEST
VREG
ST92F124/F150/F250 power supply pins
Function
LQFP64 PQFP100 LQFP100
-
18
15
Main Power Supply Voltage
(Pins internally connected)
27
42
39
-
65
62
60
93
90
-
17
14
Digital Circuit Ground
(Pins internally connected)
26
41
38
-
64
61
59
92
89
Analog Circuit Supply Voltage
49
82
79
Analog Circuit Ground
50
83
80
Must be kept low in standard operating mode
29
44
41
Stabilization capacitor(s) for internal voltage regulator 28
31
43
28
40
38/523
Doc ID 8848 Rev 7