ST92F250CV2 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST92F250CV2

8/16-bit single voltage Flash MCU family with RAM, E³ TM (emulated EEPROM), CAN 2.0B and J1850 BLPD

STMicroelectronics 

ST92F124xx/ST92F150Cxx/ST92F150JDV1/ST92F250CV2

6

Device architecture

Device architecture

6.1

Core architecture

The ST9 Core or Central Processing Unit (CPU) features a highly optimized instruction set,

capable of handling bit, byte (8-bit) and word (16-bit) data, as well as BCD and Boolean

formats; 14 addressing modes are available.

Four independent buses are controlled by the Core: a 16-bit Memory bus, an 8-bit Register

data bus, an 8-bit Register address bus and a 6-bit Interrupt/DMA bus which connects the

interrupt and DMA controllers in the on-chip peripherals with the Core.

This multiple bus architecture affords a high degree of pipelining and parallel operation, thus

making the ST9 family devices highly efficient, both for numerical calculation, data handling

and with regard to communication with on-chip peripheral resources.

6.2

6.2.1

Memory spaces

There are two separate memory spaces:

● The Register File, which comprises 240 8-bit registers, arranged as 15 groups (Group 0

to E), each containing sixteen 8-bit registers plus up to 64 pages of 16 registers

mapped in Group F, which hold data and control bits for the on-chip peripherals and

I/Os.

● A single linear memory space accommodating both program and data. All of the

physically separate memory areas, including the internal ROM, internal RAM and

external memory are mapped in this common address space. The total addressable

memory space of 4 Mbytes (limited by the size of on-chip memory and the number of

external address pins) is arranged as 64 segments of 64 Kbytes. Each segment is

further subdivided into four pages of 16 Kbytes, as illustrated in Figure 18. A Memory

Management Unit uses a set of pointer registers to address a 22-bit memory field using

16-bit address-based instructions.

Register file

The Register File consists of (see Figure 19):

● 224 general purpose registers (Group 0 to D, registers R0 to R223)

● 6 system registers in the System Group (Group E, registers R224 to R239)

● Up to 64 pages, depending on device configuration, each containing up to 16 registers,

mapped to Group F (R240 to R255), see Figure 20.

Doc ID 8848 Rev 7

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