STM32F215VGT6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STM32F215VGT6 Datasheet PDF : 173 Pages
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Electrical characteristics
STM32F21xxx
Table 65. DAC characteristics (continued)
Symbol
Parameter
Min Typ
Max
Unit
Comments
Integral non linearity
(difference between
-
-
INL(3)
measured value at Code i
and the value at Code i on a
line drawn between Code 0
-
-
and last Code 1023)
Offset error
-
-
Offset(3)
(difference between
measured value at Code
-
-
(0x800) and the ideal value =
VREF+/2)
-
-
Gain
error(3)
Gain error
-
-
Settling time (full scale: for a
10-bit input code transition
tSETTLING(3)
between the lowest and the
highest input codes when
-
3
DAC_OUT reaches final
value ±4LSB
THD(3)
Total Harmonic Distortion
Buffer ON
-
-
Max frequency for a correct
Update
rate(1)
DAC_OUT change when
small variation in the input
-
-
code (from code i to i+1LSB)
Wakeup time from off state
tWAKEUP(3) (Setting the ENx bit in the
DAC Control register)
- 6.5
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
- –67
measurement)
±1
±4
±10
±3
±12
±0.5
LSB
Given for the DAC in 10-bit
configuration.
LSB
Given for the DAC in 12-bit
configuration.
mV
Given for the DAC in 12-bit
configuration
LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V
LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V
%
Given for the DAC in 12-bit
configuration
6
µs
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
-
dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
1
MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
10
µs input code between lowest and
highest possible ones.
–40
dB No RLOAD, CLOAD = 50 pF
1. Guaranteed by design, not tested in production.
2. The quiescent mode corresponds to a state where the DAC maintains a stable output level to ensure that no dynamic
consumption occurs.
3. Guaranteed by characterization, not tested in production.
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Doc ID 17050 Rev 8
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