STM32F21xxx
Figure 72. SD default mode
Electrical characteristics
CK
D, CMD
(output)
tOVD
tOHD
5.3.28
ai14888
Table 82. SD / MMC characteristics
Symbol
Parameter
Conditions
Min
fPP
Clock frequency in data transfer
mode
CL ≤ 30 pF
0
-
SDIO_CK/fPCLK2 frequency ratio
-
-
tW(CKL) Clock low time, fPP = 16 MHz
CL ≤ 30 pF
32
tW(CKH) Clock high time, fPP = 16 MHz
CL ≤ 30 pF
31
tr
Clock rise time
CL ≤ 30 pF
tf
Clock fall time
CL ≤ 30 pF
CMD, D inputs (referenced to CK)
tISU
Input setup time
CL ≤ 30 pF
2
tIH
Input hold time
CL ≤ 30 pF
0
CMD, D outputs (referenced to CK) in MMC and SD HS mode
tOV
Output valid time
CL ≤ 30 pF
tOH
Output hold time
CL ≤ 30 pF
0.3
CMD, D outputs (referenced to CK) in SD default mode(1)
tOVD Output valid default time
CL ≤ 30 pF
tOHD Output hold default time
CL ≤ 30 pF
0.5
1. Refer to SDIO_CLKCR, the SDI clock control register to control the CK output.
Max Unit
48
MHz
8/3
-
ns
3.5
5
ns
6
ns
7
ns
RTC characteristics
Table 83. RTC characteristics
Symbol
Parameter
Conditions
Min
Max
-
fPCLK1/RTCCLK frequency ratio
Any read/write operation
from/to an RTC register
4
-
Doc ID 17050 Rev 8
141/173