STM32F217IGH6V View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STM32F217IGH6V

ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F21xxx

Electrical characteristics

Table 39. EMI characteristics

Symbol Parameter

Conditions

SEMI

Peak level

VDD = 3.3 V, TA = 25 °C, LQFP176

package, conforming to SAE J1752/3

EEMBC, code running with ART

enabled

VDD = 3.3 V, TA = 25 °C, LQFP176

package, conforming to SAE J1752/3

EEMBC, code running with ART

enabled, PLL spread spectrum

enabled

Monitored

frequency band

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI level

Max vs.

[fHSE/fCPU]

8/120 MHz

21

28

31

4

21

15

14

3.5

Unit

dBµV

-

dBµV

-

5.3.14

Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is

stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are

applied to the pins of each sample according to each pin combination. The sample size

depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test

conforms to the JESD22-A114/C101 standard.

Table 40. ESD absolute maximum ratings

Symbol

Ratings

Conditions

Class

Maximum

value(1)

Unit

VESD(HBM)

VESD(CDM)

Electrostatic discharge

voltage (human body

model)

Electrostatic discharge

voltage (charge device

model)

TA = +25 °C conforming to JESD22-A114 2

TA = +25 °C conforming to JESD22-C101 II

2000(2)

V

500

1. Based on characterization results, not tested in production.

2. On VBAT pin, VESD(HBM) is limited to 1000 V.

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Doc ID 17050 Rev 8

93/173

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