STP16CPC26
Timing diagrams
Table 7.
CLOCK
Truth table
LE
OE
Serial-IN OUT0 ........... OUT7 .............. OUT15(1) SDO
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
L
L
Dn + 1
No change
H
L
Dn + 2
Dn + 2 ..... Dn - 5 ..... Dn -13
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
X
H
Dn + 3
OFF
1. OUTn = ON when Dn = H, OUTn = OFF when Dn = L
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
Figure 12. Timing for clock signal, serial-in and serial out data
$0Y
The correct sampling of the data depends on the stability of the data at SDI on the rising
edge of the clock signal and it is assured by a proper data setup and hold time (tSETUP1 And
tHOLD), as shown in Figure 12. The same figure shows the propagation delay from CLK to
SDO (tPLH/tPHL).
Figure 13 describes the setup times for LE and OE signals (tSETUP2 and tSETUP3
respectively), the minimum duration of these signals (tWLAT and tWENA respectively) and the
propagation delay from CLK to OUTn, LE to OUTn and OE to OUTn (tPLH1/tPHL1, tPLH2/tPHL2
and tPLH3/tPHL3 respectively).
Finally Figure 14 defines the turn-on and turn-off time (tr and tf) of the current generators.
Doc ID 18469 Rev 4
13/26