ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLITE39F2U6TR
STMicroelectronics
ST7PLITE39F2U6TR Datasheet PDF : 173 Pages
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ST7LITE3xF2
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.6.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
7
0
EOC SPEED ADON 0
0 CH2 CH1 CH0
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
7
0
D9 D8 D7 D6 D5 D4 D3 D2
Bit 7:0 = D[9:2] MSB of Analog Converted Value
CONTROL AND DATA REGISTER LOW (AD-
CDRL)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
0
0
0
0 SLOW 0
D1 D0
Bit 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = Reserved. Forced by hardware to 0.
Bit 4:3 = Reserved. Must be kept cleared.
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Channel Pin*
CH2 CH1 CH0
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
*The number of channels is device dependent. Refer to
the device pinout description.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
fADC
fCPU/2
fCPU
fCPU/4
SLOW SPEED
0
0
0
1
1
x
Bit 2 = Reserved. Forced by hardware to 0.
Bit 1:0 = D[1:0] LSB of Analog Converted Value
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