ST7PLITE39F2U6TR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST7PLITE39F2U6TR
STMicroelectronics
ST7PLITE39F2U6TR Datasheet PDF : 173 Pages
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ST7LITE3xF2
DUAL 12-BIT AUTORELOAD TIMER 3 (Cont’d)
11.2.6 Register Description
TIMER CONTROL STATUS REGISTER
(ATCSR)
Read / Write
Reset Value: 0x00 0000 (x0h)
7
6
0
0
ICF ICIE CK1 CK0 OVF1 OVFIE1 CMPIE
Bit 7 = Reserved.
Bit 6 = ICF Input Capture Flag.
This bit is set by hardware and cleared by software
by reading the ATICR register (a read access to
ATICRH or ATICRL will clear this flag). Writing to
this bit does not change the bit value.
0: No input capture
1: An input capture has occurred
0: Overflow interrupt disabled.
1: Overflow interrupt enabled.
Bit 0 = CMPIE Compare Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset. It can be used to mask the
interrupt generated when any of the CMPFx bit is
set.
0: Output compare interrupt disabled.
1: Output Compare interrupt enabled.
COUNTER REGISTER 1 HIGH (CNTR1H)
Read only
Reset Value: 0000 0000 (000h)
15
8
0
0
0
0
CNTR1_ CNTR1_ CNTR1_ CNTR1_
11
10
9
8
Bit 5 = ICIE IC Interrupt Enable.
This bit is set and cleared by software.
0: Input capture interrupt disabled
1: Input capture interrupt enabled
Bits 4:3 = CK[1:0] Counter Clock Selection.
These bits are set and cleared by software and
cleared by hardware after a reset. They select the
clock frequency of the counter.
Counter Clock Selection
OFF
OFF
fLTIMER (1 ms timebase @ 8 MHz)
fCPU
CK1 CK0
0
0
1
1
0
1
1
0
Bit 2 = OVF1 Overflow Flag.
This bit is set by hardware and cleared by software
by reading the TCSR register. It indicates the tran-
sition of the counter1 CNTR1 from FFh to ATR1
value.
0: No counter overflow occurred
1: Counter overflow occurred
Bit 1 = OVFIE1 Overflow Interrupt Enable.
This bit is read/write by software and cleared by
hardware after a reset.
COUNTER REGISTER 1 LOW (CNTR1L)
Read only
Reset Value: 0000 0000 (000h)
7
0
CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_
7
6
5
4
3
2
1
0
Bits 15:12 = Reserved.
Bits 11:0 = CNTR1[11:0] Counter Value.
This 12-bit register is read by software and cleared
by hardware after a reset. The counter CNTR1 is
incremented continuously as soon as a counter
clock is selected. To obtain the 12-bit value, soft-
ware should read the counter value in two consec-
utive read operations. The CNTR1H register can
be incremented between the two reads, and in or-
der to be accurate when fTIMER=fCPU, the software
should take this into account when CNTR1L and
CNTR1H are read. If CNTR1L is close to its high-
est value, CNTR1H could be incremented before it
is read.
When a counter overflow occurs, the counter re-
starts from the value specified in the ATR1 regis-
ter.
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