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ST7PLITE35F2M6TR View Datasheet(PDF) - STMicroelectronics

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ST7PLITE35F2M6TR Datasheet PDF : 173 Pages
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ST7LITE3xF2
SERIAL PERIPHERAL INTERFACE (cont’d)
11.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 49.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see Figure 52 on page 83) but master
and slave must be programmed with the same tim-
ing mode.
Figure 49. Single Master/ Single Slave Application
MASTER
MSBit
LSBit
8-bit SHIFT REGISTER
MISO
MISO
MSBit
SLAVE
LSBit
8-bit SHIFT REGISTER
MOSI
MOSI
SPI
CLOCK
GENERATOR
SCK
SS +5V
SCK
SS
Not used if SS is managed
by software
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